Averaging circuit which determines average voltage of n samples, using log2n-scale capacitors

ABSTRACT

For example, an averaging circuit includes first to third capacitors and a controller. The controller causes a first first-stage average voltage to be applied to a first capacitor, the first first-stage average voltage being an average of a first voltage applied to the first capacitor and a second voltage applied to a second capacitor, causes a second first-stage average voltage to be applied to the second capacitor, the second first-stage average voltage being an average of a third voltage applied to the second capacitor and a fourth voltage applied to a third capacitor, and causes a first second-stage average voltage to be applied to the first capacitor, the first second-stage average voltage being an average of the first and second first-stage average voltages applied to the first and second capacitors.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2016-020691, filed Feb. 5, 2016, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to an averaging circuitwhich determines average voltage of N samples, using log₂ N-scalecapacitors.

BACKGROUND

A discrete-time wireless receiver including a switched capacitor circuithas a high configurability. The discrete-time wireless receiver needs toeliminate noise. In a high-frequency domain applied to radio, noise isprimarily thermal noise. The amplitude of noise approximates to a normaldistribution.

In the case where the amplitude of noise contained in a signalapproximates to a normal distribution, a number of signal values(samples) of the signal are sampled to determine an average value, sothat the noise (noise power) contained in the signal can be reduced.

As an averaging circuit which determines an average value of N (anatural number of 2 or more) signal values, an averaging circuitemploying N sampling switches and N capacitors is known.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an example of an averaging circuitaccording to the first embodiment.

FIG. 2 is a circuit diagram showing an example of the first stage of anoperation performed by the averaging circuit according to the firstembodiment.

FIG. 3 is a circuit diagram showing an example of the second stage ofthe operation performed by the averaging circuit according to the firstembodiment.

FIG. 4 is a circuit diagram showing an example of the third stage of theoperation performed by the averaging circuit according to the firstembodiment.

FIG. 5 is a circuit diagram showing an example of the fourth stage ofthe operation performed by the averaging circuit according to the firstembodiment.

FIG. 6 is a circuit diagram showing an example of the fifth stage of theoperation performed by the averaging circuit according to the firstembodiment.

FIG. 7 is a circuit diagram showing an example of the sixth stage of theoperation performed by the averaging circuit according to the firstembodiment.

FIG. 8 is a circuit diagram showing an example of the seventh stage ofthe operation performed by the averaging circuit according to the firstembodiment.

FIG. 9 is a circuit diagram showing an example of the eighth stage ofthe operation performed by the averaging circuit according to the firstembodiment.

FIG. 10 is a circuit diagram showing an example of the ninth stage ofthe operation performed by the averaging circuit according to the firstembodiment.

FIG. 11 is a circuit diagram showing an example of the tenth stage ofthe operation performed by the averaging circuit according to the firstembodiment.

FIG. 12 is a circuit diagram showing an example of the eleventh stage ofthe operation performed by the averaging circuit according to the firstembodiment.

FIG. 13 is a circuit diagram showing an example of a general averagingcircuit as a comparative example.

FIG. 14 is a graph showing an example of a relationship between noisepower and the number N of signal values to be equalized in the averagingcircuit according to the first embodiment.

FIG. 15 is a graph showing an example of a reduction result of a circuitarea in the averaging circuit according to the first embodiment.

FIG. 16 is a circuit diagram showing an example of a schematicconfiguration of an averaging circuit according to the secondembodiment.

FIG. 17 is a circuit diagram showing an example of a detailedconfiguration of the averaging circuit according to the secondembodiment.

FIG. 18 is a timing chart showing an example of an operation of theaveraging circuit, according to the second embodiment.

FIG. 19 is a circuit diagram showing an example of a schematicconfiguration of an averaging circuit according to the third embodiment.

FIG. 20 is a circuit diagram showing an example of a detailedconfiguration of the averaging circuit according to the thirdembodiment.

FIG. 21 is a timing chart showing an example of an operation of theaveraging circuit according to the third embodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, an averaging circuit includes acapacitor circuit and a controller which controls the capacitor circuit.The capacitor circuit includes a plurality of circuit units and aplurality of averaging switches. The circuit units includes capacitorsand sampling switches. The capacitor and sampling switch included ineach of the circuit units are connected in series to each other. Theaveraging switches switch two capacitors connected in serious among thecapacitors included in the circuit units. The controller controls thesampling switches included in the circuit units and the averagingswitches. The controller causes a first first-stage average voltage tobe applied to a first capacitor included in the circuit units. The firstfirst-stage average voltage is an average of a first sample voltageapplied to the first capacitor and a second sample voltage applied to asecond capacitor included in the circuit units. The controller causes asecond first-stage average voltage to be applied to the secondcapacitor. The second first-stage average voltage is an average of athird sample voltage applied to the second capacitor and a fourth samplevoltage applied to a third capacitor included in the circuit units. Thecontroller causes a first second-stage average voltage to be applied tothe first capacitor. The first second-stage average voltage is anaverage of the first and second first-stage average voltages applied tothe first and second capacitors.

Embodiments will be described hereinafter with reference to theaccompanying drawings. In the drawings, identical elements will bedenoted by the same reference numbers, respectively.

First Embodiment

In the first embodiment, for example, a discrete-time wireless receiverincludes a reception module which receives a given input signal N timesat intervals, a noise elimination module which determines an averagevalue of N signal values of the signal received by the reception module,to thereby eliminate noise from the signal, and a signal processor whichperforms analog/digital conversion based on the value of the signal fromwhich the noise have been eliminated.

In the following explanation of the first embodiment, an averagingcircuit included in a noise elimination module in a wireless transceiveris described by way of example; however, a device including theaveraging circuit is not limited to this.

With respect to the first embodiment, an averaging circuit whichdetermines an average value of N signal values (N is the number ofsamples) using (log₂ N)+1 capacitors will be referred to. With respectto the first embodiment, identical structural elements will be denotedby the same reference numeral, and after they are explained once, theirexplanations will be omitted or simply explained.

FIG. 1 is a circuit diagram showing an example of an averaging circuitaccording to the first embodiment.

In an example illustrated in FIG. 1, N is 8; and FIG. 1 illustrates anaveraging circuit which determines an average value of eight signalvalues using four capacitors. However, N can be changed as long as theformula N=A×2^(P) (A is 1, 2 or 3, and P is a natural number) issatisfied.

The averaging circuit 1 includes a switched capacitor circuit 2 and acontroller 3.

The switched capacitor circuit 2 includes four sampling switches S₁ toS₄, four capacitors C₁ to C₄ and three averaging switches A₁ to A₃. Inthe first embodiment, a sampling switch and a capacitor which areconnected in series to each other may be handled as a single circuitunit.

The averaging circuit 1 includes four sampling switches S₁ to S₄, fourcapacitors C₁ to C₄ and three averaging switches A₁ to A₃.

One end of sampling switch S₁ is connected to input terminal I, and theother end of sampling switch S₁ is connected to one end of capacitor C₁.The other end of capacitor C₁ is grounded.

The same is true of sampling switches S₂ to S₄ and capacitors C₂ to C₄;that is, sampling switches S₂ to S₄ and capacitors C₂ to C₄ are set inthe same manner as sampling switch S₁ and capacitor C₁.

Ends of averaging switches A₁ to A₃ are respectively connected to endsof sampling switches S₁ to S₃ and ends of capacitors C₁ to C₃. The otherends of averaging switches A₁ to A₃ are respectively connected to theabove ends of sampling switches S₂ to S₄ and the above ends ofcapacitors C₂ to C₄.

The capacitances of capacitors C₁ to C₄ are equal to each other.

Output terminal O is connected to one end of one of capacitors C₁ andC₂. In the example illustrated in FIG. 1, output terminal O is connectedto one end of capacitor C₁.

The controller 3, as described later, produces control signals foreffecting switching between ON and OFF states (closing and opening) ofeach of sampling switches S₁ to S₄ and switching between ON and OFFstates (closing and opening) of each of averaging switches A₁ to A₃.

With reference to FIGS. 2 to 12, it will be explained how the averagingcircuit 1 is operated to determine an average value. FIGS. 2 to 12illustrate the states of the switches at respective stages, omitting thecontroller 3 for simplicity.

FIG. 2 is a circuit diagram showing an example of the first stage of anoperation performed by the averaging circuit 1 according to the firstembodiment.

The averaging circuit 1 determines an average value of signal values ofinput signal D_(I) input from input terminal I. The voltage of inputsignal D_(I) varies with the passage of time.

At the first stage, the controller 3 opens (turns off) sampling switchesS₁ to S₄ and averaging switches A₁ to A₃. At this time, the voltagesapplied to capacitors C₁ to C₄ are zero.

FIG. 3 is a circuit diagram showing an example of the second stage ofthe operation performed by the averaging circuit 1 according to thefirst embodiment.

At the second stage, the controller 3 closes (turns on) sampling switchS₂. Thereby, voltage V₁ of input signal D_(I) at time t₁ is applied tocapacitor C₂ connected in series to sampling switch S₂. The voltageobtained based on input signal D_(I) will be referred to as the samplingvoltage.

FIG. 4 is a circuit diagram showing an example of the third stage of theoperation performed by the averaging circuit 1 according to the firstembodiment.

At the third stage, the controller 3 opens sampling switch S₂, and thencloses sampling switch S₁. Thereby, voltage V₂ of input signal D_(I) attime t₂ is applied to capacitor C₁ connected in series to samplingswitch S₁.

FIG. 5 is a circuit diagram showing an example of the fourth stage ofthe operation performed by the averaging circuit 1 according to thefirst embodiment.

At the fourth stage, the controller 3 opens sampling switch S₁, and thencloses sampling switch S₃ and averaging switch A₁. Thereby, voltage V₃of input signal D_(I) at time t₃ is applied to capacitor C₃ connected inseries to sampling switch S₃. Furthermore, voltages applied to bothcapacitors C₁ and C₂ are equalized (their average is determined) and areeach set to (V₁+V₂)/2.

FIG. 6 is a circuit diagram showing an example of the fifth stage of theoperation performed by the averaging circuit 1 according to the firstembodiment.

At the fifth stage, the controller 3 opens sampling switch S₃ andaveraging switch A₁, and resets the voltage applied to capacitor C₂(sets the voltage to zero). Then, the controller 3 closes samplingswitch S₂. Thereby, voltage V₄ of input signal D_(I) at time t₄ isapplied to capacitor C₂ connected in series to sampling switch S₂.

FIG. 7 is a circuit diagram showing an example of the sixth stage of theoperation performed by the averaging circuit 1 according to the firstembodiment.

At the sixth stage, the controller 3 opens sampling switch S₂, and thencloses averaging switch A₂. Thereby, voltages applied to both capacitorsC₂ and C₃ are equalized (their average is determined) and are each setto (V₃+V₄)/2.

FIG. 8 is a circuit diagram showing an example of the seventh stage ofthe operation performed by the averaging circuit 1 according to thefirst embodiment.

At the seventh stage, the controller 3 opens averaging switch A₂, andthen closes averaging switch A₁. Thereby, voltages applied to bothcapacitors C₁ and C₂ are equalized (averaged out) and are each set to(V₁+V₂+V₃+V₄)/2.

FIG. 9 is a circuit diagram illustrating by way of example the eighthstage of the operation of the averaging circuit 1 according to the firstembodiment.

At the eighth stage, the controller 3 opens averaging switch A₁, andthen resets the voltages applied to capacitors C₂ and C₃ (sets thevoltages to zero).

FIG. 10 is a circuit diagram showing an example of the ninth stage ofthe operation performed by the averaging circuit 1 according to thefirst embodiment.

At the ninth stage, the controller 3 performs the same control oversampling switches S₂ to S₄ and averaging switches A₂ and A₃ as oversampling switches S₁ to S₃ and averaging switches A₁ and A₂ at the firstto eighth stages as illustrated in FIGS. 2 to 9.

FIG. 11 is a circuit diagram showing an example of the tenth stage ofthe operation performed by the averaging circuit 1 according to thefirst embodiment.

At the tenth stage, the voltage applied to capacitor C₁ is varied to(V₁+V₂+V₃+V₄)/4, and the voltage applied to capacitor C₂ is varied to(V₅+V₆+V₇+V₈)/4. It should be noted that voltages V₅ to V₈ are voltagesof input signal D_(I) at time t₅ to t₈, respectively. The voltagesapplied to capacitors C₃ and C₄ are changed to zero.

FIG. 12 is a circuit diagram showing an example of the eleventh stage ofthe operation performed by the averaging circuit 1 according to thefirst embodiment.

At the eleventh stage, the controller 3 closes averaging switch A₁.Thereby, voltages applied to both capacitors C₁ and C₂ are equalized andare each set to (V₁+V₂+V₃+V₄+V₅+V₆+V₇+V₈)/8.

The controller 3 causes charge accumulated in either capacitor C₁ or C₂to be output from output terminal O. As a result, a voltage having theaverage value of the voltages of input signal D_(I) at time t₁ to t₈ canbe output.

It should be noted that the above second and third stages may be appliedin reverse order. That is, it may be set that at the second stage, thecontroller 3 closes sampling switch S₁ to apply voltage V₁ to capacitorC₁, and at the third stage, the controller 3 closes sampling switch S₂to apply voltage V₂ to capacitor C₂. In this case, at the fourth stage,the controller 3 opens sampling switch S₂, and then closes samplingswitch S₃ and averaging switch A₁.

Furthermore, it may be set that in the above fourth and fifth stages,the controller 3 determines the average of the voltages applied to bothcapacitors C₁ and C₂, and resets the voltage applied to capacitor C₂(sets it to zero); and then causes voltage V₃ to be applied to capacitorC₃ by closing sampling switch S₃, and voltage V₄ to be applied tocapacitor C₂ by closing sampling switch S₂. In this case, samplingswitch S₃ and sampling switch S₂ may be operated in reverse order. Thatis, it may be set that sampling switch S₂ is closed to apply voltage V₃to capacitor C₂, and sampling switch S₃ is closed to apply voltage V₄ tocapacitor C₃.

Furthermore, the above operation of resetting the voltage applied tocapacitor C₃ (setting it to zero) at the eighth stage may be performedat any time before the seventh stage is started after determining theaverage of the voltages applied to both capacitors C₂ and C₃ at thesixth stage.

The advantage of the averaging circuit 1 according to the firstembodiment, which has the structure as described above, will beexplained.

FIG. 13 is a circuit diagram showing an example of a general averagingcircuit, which will be described as a comparative example. The averagingcircuit 100 determines the average value of N signal values. In thiscase, the averaging circuit 100 includes N sampling switches S₁ toS_(N), N capacitors C₁ to C_(N) and N−1 averaging switches A₁ toA_(N-1).

One end of sampling switch S₁ is connected to input terminal I, and theother end of sampling switch S₁ is connected to one end of capacitor C₁.The other end of capacitor C₁ is grounded.

The same is true of sampling switches S₂ to S_(N) and capacitors C₂ toC_(N); that is, sampling switches S₂ to S_(N) and capacitors C₂ to C_(N)are set in the same manner as sampling switch S₁ and capacitor C₁.

Ends of averaging switches A₁ to A_(N-1) are respectively connected toends of sampling switches S₁ to S_(N-1) and ends of capacitors C₁ toC_(N-1). The other ends of averaging switches A₁ to A_(N-1) arerespectively connected to the above ends of sampling switches S₂ toS_(N) and the above ends of capacitors C₂ to C_(N).

The capacitances of capacitors C₁ to C_(N) are equal to each other.

Output terminal O is connected to any of averaging switches A₁ toA_(N-1).

First, the averaging circuit 100 opens sampling switches S₁ to S_(N),and also opens averaging switches A₁ to A_(N-1).

Next, the averaging circuit 100 closes only sampling switch S₁ toaccumulate in capacitor C₁, charge input from input terminal I.

Subsequently, the averaging circuit 100 opens sampling switch S₁ andcloses sampling switch S₂ to accumulate in capacitor C₂, charge inputfrom input terminal I.

Thereafter, in the same manner as described above, charge input frominput terminal I is accumulated in capacitors C₃ to C_(N) successively.

Then, the averaging circuit 100 open sampling switches S₁ to S_(N) andclose averaging switches A₁ to A_(N-1) to equalize the voltages appliedto capacitors C₁ to C_(N), (determine the average of the voltages) i.e.,equalize charge accumulated in capacitors C₁ to C_(N). The averagingcircuit 100 outputs the equalized charge from any of capacitors C₁ toC_(N) through output terminal O.

In the averaging circuit 100, the greater the number N of signal valuesto be equalized (signal values the average of which is to bedetermined), the greater the number of sampling switches S₁ to S_(N),that of capacitors C₁ to C_(N) and that of averaging switches A₁ toA_(N-1). Therefore, the greater the number N of signal values to beequalized, the greater the area of the averaging circuit 100.

FIG. 14 is a graph showing an example of a relationship between noisepower and the number N of signal values to be equalized in the averagingcircuit 1 according to the first embodiment.

In both a theoretical value and the result of a simulation such as onedone with Simulation Program with Integrated Circuit Emphasis (SPICE),the greater the number N of signal values to be equalized, the lower thenoise power. To be more specific, N signal values are equalized (theaverage of these signal values is determined), so that noise power canbe reduced to 1/N.

FIG. 15 is a graph showing an example of a reduction result of a circuitarea, i.e., the area of the averaging circuit 1 according to the firstembodiment.

In an ordinary averaging circuit 100, the greater the number N of signalvalues to be equalized, the greater the number of capacitors included inthe averaging circuit 100. Inevitably, the circuit area is increased inproportion to the increase in the number of capacitors. By contrast, inthe averaging circuit 1 according to the first embodiment, the number M(M is a natural number of 2 or more) of capacitors can be reduced to(log₂ N)+1. That is, in the first embodiment, even if the number N ofsignal values is increased, it is restricted that the circuit area isincreased.

The averaging circuit 1 according to the first embodiment is used toreduce noise in, for example, a wireless receiver. With respect to theaveraging circuit 1, the average of N signal values can be determined ina circuit area which varies in proportion to (log₂ N)+1, and is smallerthan a circuit area varying in proportion to N. For example, whereN=128, the area of the averaging circuit 1 can be reduced byapproximately 94% of the area of the ordinary averaging circuit.

It should be noted that the above explanation of the first embodiment isgiven with respect to the case where the average of signal values isdetermined under a condition in which capacitors C₁ to C_(M) have thesame capacitance. However, if a plurality of capacitors, which areprovided such that ends of the capacitors are connected to inputterminal I, with switches interposed between the ends of the capacitorsand the input terminal, and the other ends of the capacitors aregrounded, have different capacitances which depend on the values ofweighting coefficients, respectively, they can be applied to anotherkind of circuit such as a finite impulse response (FIR) filter.

Second Embodiment

The second embodiment will be explained by referring to the averagingcircuit according to the first embodiment in detail. In the following,the explanations given above with reference to FIGS. 1 to 15 are notrepeated.

FIG. 16 is a circuit diagram showing an example of a schematicconfiguration of an averaging circuit 1 according to the secondembodiment.

FIG. 17 is a circuit diagram showing an example of a detailedconfiguration of the averaging circuit 1 according to the secondembodiment.

The averaging circuit 1 includes M sampling switches S₁ to S_(M) and Mcapacitors C₁ to C_(M), M−1 averaging switches A₁ to A_(M-1), M resetswitches R₁ to R_(M), reset switches R₁ to R_(M), output switch S_(OUT)and output capacitor C_(OUT).

Ends of reset switches R₁ to R_(M) are connected to ends of capacitorsC₁ to C_(M), respectively. The other ends of reset switches R₁ to R_(M)are grounded.

When reset switches R₁ to R_(M) are closed (turned on), chargeaccumulated in capacitors C₁ to C_(M) is reset so that the capacitancesof capacitors C₁ to C_(M) are set to zero. The controller 3, asdescribed later, produces control signals for effecting switchingbetween ON and OFF states (closing and opening) of each of samplingswitches S₁ to S₄ and switching between ON and OFF states (closing andopening) of each of averaging switches A₁ to A₃.

An end of output switch S_(OUT) is connected to an end of samplingswitch S₁ and an end of capacitor C₁. The other end of output switchS_(OUT) is connected to an end of output capacitor C_(OUT) and outputterminal O. The other end of output capacitor C_(OUT) is grounded.

When output switch S_(OUT) is closed, output signal D₀ is output fromoutput terminal O.

The controller 3, as described later, produces control signals foreffecting switching between ON and OFF states (closing and opening) ofeach of sampling switches S₁ to S_(M), each of averaging switches A₁ toA_(M-1), each of reset switches R₁ to R_(M), and output switch S_(OUT).

FIG. 18 is a timing chart illustrating an example of the operation ofthe averaging circuit 1 according to the second embodiment. FIG. 18illustrates by way of example the case where sampling switches S₁ to S₃,averaging switches A₁ and A₂ and reset switches R₁ to R₃ are opened andclosed, so that an average value of N (N=4) signal values is determined.

It should be noted that where N=8, an average value (first averagevalue) of four signals is determined by opening and closing samplingswitches S₁ to S₃, averaging switches A₁ to A₃ and reset switches R₁ andR₂, and an average value (second average value) of other four signals isdetermined by opening and closing sampling switches S₂ to S₄, averagingswitches A₂ to A₄ and reset switches R₂ and R₃; and an average value ofthe first average value and the second average value is furtherdetermined.

Also, where N=12 or more, 12 or more signals are divided into three ormore groups, an average value of four signal values belonging to each ofthe three or more groups is determined, that is, average values of thethree or more groups are successively determined; and an average valueof the determined average values of the three or more groups is thendetermined.

The controller 3 operates in response to a clock signal CLK. The clocksignal CLK repeatedly changes between high and low. This will beexplained in detail as follows:

When first clock signal CLK1 is high, the controller 3 closes (turns on)sampling switch S₂. Thereby, voltage V₁ is applied to capacitor C₂.

When second clock signal CLK2 is high, the controller 3 closes samplingswitch S₁. Thereby, voltage V₂ is applied to capacitor C₁.

When third clock signal CLK3 is high, the controller 3 closes averagingswitch A₁ and sampling switch S₃. Thereby, voltage (V₁+V₂)/2 is appliedto capacitors C₁ and C₂, and voltage V₃ is applied to capacitor C₃.

In a period between a period which third clock signal CLK3 is high and aperiod in which fourth clock signal CLK4 is high (when third clocksignal CLK3 becomes low), the controller 3 closes reset switch R₂.Thereby, the voltage of capacitor C₂ is reset.

When fourth clock signal CLK4 is high, the controller 3 closes samplingswitch S₂. Thereby, voltage V₄ is applied to capacitor C₂.

When fifth clock signal CLK5 is high, the controller 3 closes averagingswitch A₂. Thereby, voltage (V₃+V₄)/2 is applied to capacitors C₂ andC₃.

In a period between a period in which fifth clock signal CLK5 is highand a period in which sixth clock signal CLK6 is high (when fifth clocksignal CLK5 becomes low), the controller 3 closes reset switch R₃.Thereby, the voltage of capacitor C₃ is reset.

When sixth clock signal CLK6 is high, the controller 3 closes averagingswitch A₁ and output switch S_(OUT). Thereby, voltage (V₁+V₂+V₃+V₄)/4 isapplied to capacitors C₂ and C₃, and an output signal corresponding tovoltage (V₁+V₂+V₃+V₄)/4 is output from output terminal O.

In a period between a period in which sixth clock signal CLK6 is highand a period in which seventh clock signal CLK7 is high (when sixthclock signal CLK6 becomes low), the controller 3 closes reset switch R₂.Thereby, the voltage of capacitor C₂ is reset.

An algorithm which is applied in the controller 3 according to thesecond embodiment will be explained.

k is a natural number which satisfies the formula 0<k≦N.

In the case where k=a₀·2⁰+a₁·2¹+ . . . +a_(P)·2^(P) (P is a naturalnumber), X(k) is expressed by formula (1) below.

X(k)=Σ_(q=0) ^(P) a _(q)  (1)

For example, where k=5, if 5 is expressed in a binary number, it is 101.In this case, X(5) is 2.

First, sampling of voltage V_(k) will be explained. It should be notedthat in the second embodiment, it will be referred to as sampling that avoltage corresponding to an input signal is applied to a capacitor.

Where k is an odd number, the controller 3 closes X(k)+1^(th) samplingswitch S_(X(k)+1) to apply voltage V_(k) to X(k)+1^(th) capacitorC_(X(k)+1).

Where k is an even number, the controller 3 closes X(k−1)^(th) samplingswitch S_(X(k−1)) to apply voltage V_(k) to X(k−1)^(th) capacitorC_(X(k−1)).

Then, equalization will be explained.

The controller 3 performs first to third controls, which will beexplained below, over averaging switches A₁ to A_(M-1).

In the first control, in the case where k is a multiple of 2, aftercompletion of k^(th) sampling and before completion of k+1^(th)sampling, the controller 3 closes X(k−1)^(th) averaging switchA_(X(k−1)) to equalize voltages applied to X(k−1)^(th) capacitorC_(X(k−1)) and X(k−1)+1^(th) capacitor C_(X(k−1)+1).

In the second control, in the case where k is a multiple of 4, beforecompletion of k+1^(th) sampling, the controller 3 closes X(k−1)−1^(th)averaging switch A_(X(k−1)−1), and equalizes voltages applied toX(k−1)−1^(th) capacitor C_(X(k−1)−1) and X(k−1)^(th) capacitorC_(X(k−1)). The second control over an averaging switch is performedafter the first control over the averaging switch.

In the third control, in the case where k is a multiple of an exponentof 2 (2^(P)), before completion of sampling of k+1^(th) sampling, thecontroller 3 closes X(k−1)+1−P^(th) averaging switch A_(X(k−1)+1−P), andequalizes voltages applied to X(k−1)+1−P^(th) capacitor C_(X(k−1)+1−P)and X(k−1)+2−P^(th) capacitor C_(X(k−1)+2−P). The third control over anaveraging switch is performed after the second control over theaveraging switch. It should be noted that the above operation isperformed on all values of P in the ascending order of the value of P.

For example, if an averaging switch satisfies execution conditions forexecution of a plurality of controls which are included in the abovefirst to third controls (for example, an execution condition in which kis 2 or 4), and the plurality of controls have the same processingcontent, only one of the controls is performed.

As described above, if an averaging switch satisfies executionconditions for execution of a plurality of controls which are includedin the above first to third controls (for example, an executioncondition in which k is 8 or 16), and the plurality of controls havedifferent processing content, the third control is performed after thefirst and second controls.

Next, it will be explained how a capacitor is reset.

After the controller 3 closes X(k−1)^(th) averaging switch A_(X(k−1)),before starting k+1^(th) sampling, the controller 3 closes X(k−1)+1^(th)reset switch R_(X(K−1)+1) to discharge capacitor C_(X(k−1)+1).

After the above operation is completed, the controller 3 increments thevalue of k by 1, and also performs sampling of voltage V_(k+1). When kbecomes greater than N, the sampling is ended.

To be more specific, for example, if k is 16, it is a multiple of 2, andthe execution condition for the above first control is thus satisfied.Also, since k is a multiple of 4, the execution condition for the secondcontrol is satisfied. In addition, since k is a multiple of 2³ and 2⁴,and P=3 and 4, the execution condition for the third control issatisfied. Therefore, the first to third controls are successivelyperformed in the following manner.

First, in the first control, averaging switch A₄ is closed to equalizethe voltages applied to capacitors C₄ and C₅.

Next, in the second control, averaging switch A₃ is closed to equalizethe voltages applied to capacitors C₃ and C₄.

Furthermore, in the third control, as a control to be performed in thecase where P=3, averaging switch A₂ is closed to equalize the voltagesapplied to capacitors C₂ and C₃. Subsequently, as a control to beperformed in the case where P=4, averaging switch A₁ is closed toequalize the voltages applied to capacitor C₁ and C₂.

After the operations of the above first to third controls, thecontroller 3 increments the value of k by 1, and performs sampling ofvoltage V₁₇.

As described above, in the averaging circuit 1 according to the secondembodiment, the circuit area can be effectively reduced as explainedwith respect to the first embodiment.

Third Embodiment

The third embodiment will be explained by referring to a modification ofthe averaging circuit according to each of the first and secondembodiments. In the following, the explanations given above withreference to FIGS. 1 to 18 are not repeated.

FIG. 19 is a circuit diagram showing an example of a schematicconfiguration of an averaging circuit 1A according to the thirdembodiment.

FIG. 20 is a circuit diagram showing an example of a detailedconfiguration of the averaging circuit 1A according to the thirdembodiment.

The averaging circuit 1A includes M sampling switches S₁ to S_(M) and Mcapacitors C₁ to C_(M), M averaging switches A₁ to A_(M), M resetswitches R₁ to R_(M), output switch S_(OUT) and output capacitorC_(OUT).

In the third embodiment, sampling switches S₁ to S_(M), capacitors C₁ toC_(M) and reset switches R₁ to R_(M) are formed to have the samestructures as those in the first embodiment and the second embodiment.

In the third embodiment, ends of averaging switches A₁ to A_(M) areconnected to ends of capacitors C₁ to C_(M), respectively. The otherends of averaging switches A₁ to A_(M) are connected to one end ofoutput switch S_(OUT). The other end of output switch S_(OUT) isconnected to one end of output capacitor C_(OUT) and output terminal O.The other end of output capacitor C_(OUT) is grounded.

When output switch S_(OUT) is closed, output signal D₀ is output fromoutput terminal O.

FIG. 21 is a timing chart showing an example of an operation of theaveraging circuit 1A according to the third embodiment. To be morespecific, FIG. 21 shows by way of example the case where samplingswitches S₁ to S₃, averaging switches A₁ to A₃ and reset switches R₁ toR₃ are opened and closed, so that an average value of N signals (N=4) isdetermined.

It should be noted that where N=8, an average value (first averagevalue) of four signals is determined by opening and closing samplingswitches S₁ to S₃, averaging switches A₁ to A₃ and reset switches R₁ toR₃, and an average value (second average value) of other four signals isdetermined by opening and closing sampling switches S₂ to S₄, averagingswitches A₂ to A₄ and reset switches R₂ to R₄; and an average value ofthe first average value and the second average value is furtherdetermined.

Also, where N=12 or more, 12 or more signals are divided into three ormore groups, an average value of four signal values belonging to each ofthe three or more groups is determined, that is, average values of thethree or more groups are successively determined; and an average valueof the determined average values of the three or more groups is thendetermined.

The controller 3A operates in response to a clock signal CLK. The clocksignal CLK repeatedly changes between high and low. This will beexplained in detail as follows:

When first clock signal CLK1 is high, the controller 3A closes samplingswitch S₂. Thereby, voltage V₁ is applied to capacitor C₂.

When second clock signal CLK2 is high, the controller 3A closes samplingswitch S₁. Thereby, voltage V₂ is applied to capacitor C₁.

When third clock signal CLK3 is high, the controller 3A closes averagingswitches A₁ and A₂ and sampling switch S₃. Thereby, voltage (V₁+V₂)/2 isapplied to capacitors C₁ and C₂, and voltage V₃ is applied to capacitorC₃.

In a period between a period which third clock signal CLK3 is high and aperiod in which fourth clock signal CLK4 is high (when third clocksignal CLK3 becomes low), the controller 3A closes reset switch R₂.Thereby, the voltage of capacitor C₂ is reset.

When fourth clock signal CLK4 is high, the controller 3A closes samplingswitch S₂. Thereby, voltage V₄ is applied to capacitor C₂.

When fifth clock signal CLK5 is high, the controller 3A closes averagingswitches A₂ and A₃. Thereby, voltage (V₃+V₄)/2 is applied to capacitorsC₂ and C₃.

In a period between a period which fifth clock signal CLK5 is high and aperiod in which sixth clock signal CLK6 is high (when fifth clock signalCLK5 becomes low), the controller 3A closes reset switch R₃. Thereby,the voltage of capacitor C₃ is reset.

When sixth clock signal CLK6 is high, the controller 3A closes averagingswitches A₁ and A₂ and output switch S_(OUT). Thereby, voltage(V₁+V₂+V₃+V₄)/4 is applied to capacitors C₂ and C₃, and an output signalcorresponding to voltage (V₁+V₂+V₃+V₄)/4 is output from output terminalO.

In a period between a period which sixth clock signal CLK6 is high and aperiod in which seventh clock signal CLK7 is high (when sixth clocksignal CLK6 becomes low), the controller 3A closes reset switch R₂.Thereby, the voltage of capacitor C₂ is reset.

An algorithm which is applied in the controller 3A according to thethird embodiment will be explained.

k, P and X(k) are the same as those in the second embodiment.

Sampling of voltage V_(k) is also the same as in the second embodiment.

Next, equalization will be explained.

The controller 3A performs first to third controls, which will beexplained below, over averaging switches A₁ to A_(M).

In the first control, in the case where k is a multiple of 2, aftercompletion of k^(th) sampling and before completion of k+1^(th)sampling, the controller 3A closes X(k−1)^(th) averaging switchA_(X(k−1)) and X(k−1)+1^(th) averaging switch A_(X(k−1)+1) to equalizethe voltages applied to X(k−1)^(th) capacitor C_(X(k−1)) andX(k−1)+1^(th) capacitor C_(X(k−1)+1).

In the second control, in the case where k is a multiple of 4, beforecompletion of k+1^(th) sampling, the controller 3A closes X(k−1)−1^(th)averaging switch A_(X(k−1)−1) and X(k−1)^(th) averaging switchA_(X(k−1)) to equalize the voltages applied to X(k−1)−1^(th) capacitorC_(X(k−1)−1) and X(k−1)^(th) capacitor C_(X(k−1)). The second controlover an averaging switch is performed after the first control over theaveraging switch.

In the third control, in the case where k is a multiple of an exponentof 2 (2^(P)), before completion of sampling of k+1^(th) sampling, thecontroller 3A closes X(k−1)+1−P^(th) averaging switch A_(X(k−1)+1−P) andX(k−1)+2−P^(th) averaging switch A_(X(k−1)+2−P) to equalize voltagesapplied to X(k−1)+1−P^(th) capacitor C_(X(k−1)+1−P) and X(k−1)+2−P^(th)capacitor C_(X(k−1)+2−P). The third control over an averaging switch isperformed after the second control over the averaging switch. It shouldbe noted that the above operation is performed on all values of P in theascending order of the value of P.

It should be noted that in the third embodiment, if an averaging switchsatisfies execution conditions for execution of a plurality of controlswhich are included in the above first to third controls, and theplurality of controls have the same processing content, only one of thecontrols is performed as in the second embodiment.

Next, it will be explained how a capacitor is reset.

After the controller 3A closes X(k−1)^(th) averaging switch A_(X(k−1)),before starting k+1^(th) sampling, the controller 3A closesX(k−1)+1^(th) reset switch R_(X(K−1)+1) to discharge capacitorC_(X(k−1)+1).

After completion of the above operation, the controller 3A incrementsthe value of k by 1, and also performs sampling of voltage V_(k+1). Whenk becomes greater than N, the sampling is ended.

In the averaging circuit 1A as explained above, the circuit area can beeffectively reduced as in the first and second embodiments.

Furthermore, in the third embodiment, M averaging switches A₁ to A_(M)are assigned to M capacitors C₁ to C_(M), respectively. Thereby, asingle set of switches, i.e., a reset switch, a sampling switch and anaveraging switch, are assigned to a single capacitor, thus clarifyingthe relationship between circuit elements.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. An averaging circuit comprising a capacitorcircuit and a controller which controls the capacitor circuit, whereinthe capacitor circuit comprises: a plurality of circuit units includingcapacitors and sampling switches, the capacitor and sampling switchincluded in each of the circuit units being connected in series to eachother; and a plurality of averaging switches which switch two capacitorsconnected in serious among the capacitors included in the circuit units,and the controller, by controlling the sampling switches included in thecircuit units and the averaging switches, performs an operation to:cause a first first-stage average voltage to be applied to a firstcapacitor included in the circuit units, the first first-stage averagevoltage being an average of a first sample voltage applied to the firstcapacitor and a second sample voltage applied to a second capacitorincluded in the circuit units; cause a second first-stage averagevoltage to be applied to the second capacitor, the second first-stageaverage voltage being an average of a third sample voltage applied tothe second capacitor and a fourth sample voltage applied to a thirdcapacitor included in the circuit units; and cause a first second-stageaverage voltage to be applied to the first capacitor, the firstsecond-stage average voltage being an average of the first and secondfirst-stage average voltages applied to the first and second capacitors.2. The averaging circuit of claim 1, wherein the controller furtherperforms an operation to: cause a third first-stage average voltage tobe applied to the second capacitor, the third first-stage averagevoltage being an average of a fifth sample voltage applied to the secondcapacitor and a sixth sample voltage applied to the third capacitor;cause a fourth first-stage average voltage to be applied to the thirdcapacitor, the fourth first-stage average voltage being an average of aseventh sample voltage applied to the third capacitor and an eighthsample voltage applied to a fourth capacitor included in the circuitunits; cause a second second-stage average voltage to be applied to thesecond capacitor, the second second-stage average voltage being anaverage of the third and fourth first-stage average voltages applied tothe second and third capacitors; and cause a third-stage average voltageto be applied to the first capacitor, the third-stage average voltagebeing an average of the first second-stage average voltage applied tothe first capacitor and the second second-stage average voltage appliedto the second capacitor.
 3. The averaging circuit of claim 1, wherein:where N is a natural number of A×2^(P), A is any of 1, 2 and 3, P is anatural number, and M is (log₂ N)+1, the capacitor circuit comprises thefirst to M^(th) capacitors; the controller controls voltage applying andresetting to the first to M^(th) capacitors, and controls averaging ofvoltages applied to two of the first to M^(th) capacitors; and thecontroller causes the first to N^(th) sample voltages to be selectivelyapplied to the first to M^(th) capacitors, determines an average voltageof two sample voltages, repeats to determine an average voltage of twoaverage voltages corresponding to a same sample voltage number, anddetermines an average value of the first to N^(th) sample voltages. 4.An averaging circuit comprising a capacitor circuit and a controller,wherein: the capacitor circuit comprises first to third samplingswitches, first to third capacitors, first and second averaging switchesand first to third reset switches, one end of each of the first to thirdsampling switches being connected to an input terminal; one end of thefirst capacitor is connected to the other end of the first samplingswitch, the other end of the first capacitor is grounded, one end of thesecond capacitor is connected to the other end of the second samplingswitch, the other end of the second capacitor is grounded, one end ofthe third capacitor is connected to the other end of the third samplingswitch, and the other end of the third capacitor is grounded; one end ofthe first averaging switch is connected to the one end of the firstcapacitor, the other end of the first averaging switch is connected tothe one end of the second capacitor, one end of the second averagingswitch is connected to the one end of the second capacitor, and theother end of the second averaging switch is connected to the one end ofthe third capacitor; one end of the first reset switch is connected tothe one end of first capacitor, the other end of the first reset switchis grounded, one end of the second reset switch is connected to the oneend of the second capacitor, the other end of the second reset switch isgrounded, one end of the third reset switch is connected to the one endof the third capacitor, and the other end of the third reset switch isgrounded; the controller operates the first and second sampling switchesto apply a first voltage to one of the first and second capacitors andapply a second voltage to the other of the first and second capacitors;operates the first averaging switch to set a voltage applied to thefirst capacitor to an average voltage of the first and second voltages,and operates the second reset switch to discharge the second capacitor;the controller operates the second and third sampling switches to applya third voltage to one of the second and third capacitors and apply afourth voltage to the other of the second and third capacitors; operatesthe second averaging switch to set a voltage applied to the secondcapacitor to an average voltage of the third and fourth voltages; andoperates the third reset switch to discharge the third capacitor; andthe controller operates the first averaging switch to set a voltageapplied to the first capacitor to an average voltage of the first tofourth voltages, and operates the second reset switch to discharge thesecond capacitor.
 5. An averaging circuit comprising a capacitor circuitand a controller, wherein: the capacitor circuit comprises first tothird sampling switches, first to third capacitors, first to thirdaveraging switches and first to third reset switches, one end of each ofthe first to third sampling switches being connected to an inputterminal; one end of the first capacitor is connected to the other endof the first sampling switch, the other end of the first capacitor isgrounded, one end of the second capacitor is connected to the other endof the second sampling switch, the other end of the second capacitor isgrounded, one end of the third capacitor is connected to the other endof the third sampling switch, and the other end of the third capacitoris grounded; one end of the first averaging switch is connected to theone end of the first capacitor, the other end of the first averagingswitch is connected to an output terminal, one end of the secondaveraging switch is connected to the one end of the second capacitor,the other end of the second averaging switch is connected to the outputterminal, one end of the third averaging switch is connected to the oneend of the third capacitor, and the other end of the third averagingswitch is connected to the output terminal; one end of the first resetswitch is connected to the one end of the first capacitor, the other endof the first reset switch is grounded, one end of the second resetswitch is connected to the one end of the second capacitor, the otherend of the second reset switch is grounded, one end of the third resetswitch is connected to the one end of the third capacitor, and the otherend of the third reset switch is grounded; the controller operates thefirst and second sampling switches to apply a first voltage to one ofthe first and second capacitors and apply a second voltage to the otherof the first and second capacitors; operates the first and secondaveraging switches to set a voltage applied to the first capacitor to anaverage voltage of the first and second voltages, and operates thesecond reset switch to discharge the second capacitor; the controlleroperates the second and third sampling switches to apply a third voltageto one of the second and third capacitors and apply a fourth voltage tothe other of the second and third capacitors; operates the secondaveraging switch to set a voltage applied to the second capacitor to anaverage voltage of the third and fourth voltages; and operates the thirdreset switch to discharge the third capacitor; and the controlleroperates the first and second averaging switches to set a voltageapplied to the first capacitor to an average voltage of the first tofourth voltages, and operates the second reset switch to discharge thesecond capacitor.